1. Field of the Invention
The present invention relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15. Also, Jin et al., U.S. Patent Application Publication No. US 2009/0184360, describe a vertical NAND string structure using SONOS charge storage technology to implement data storage cites on two sides of each vertical channel structure.
However, there is a limit on the number of layers of cells that can be implemented using vertical NAND string structures, which is imposed by the impedance of the vertical string of cells in each NAND string. Thus, the number of layers that can be practically implemented in this structure is relatively small.
As the need for higher and higher memory capacity in integrated circuit memory devices continues to increase, it is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements that can be erased and programmed.